FLEXIBLE ARCHITECTURE FOR PROCESSING ATM ADAPTATION LAYER PROTOCOLS (AAL1-5)

Arantza Antón - Eugenio V. Bonet - Dave de Vries - Sonia H. de Groot

   This work highlights the design of the transmitter part of a flexible and high-speed architecture for processing the ATM Adaptation Layer (AAL) protocols that have been standardised up to now (AAL1, AAL3/4 and AAL5). The proposed architecture adopts as a starting point the scaleable architecture for AAL type 5 presented in previous papers. In the extended architecture, we can find new blocks as well as some modifications in a few of the existing blocks in order to perform the functions required for AAL type 1 and 3/4 protocols. Special attention is given to the hardware implementation of the more critical parts of the initial AAL5 architecture like the segmentation, ATM cell builder and a low level interface with the ATM layer. VHDL has been used in the descriptions of the blocks and SYNOPSYS in the synthesis process.

Keywords: ATN sender, AAL, high speed, segmentation, VHDL

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