DESIGN OF A RISC MICROCONTROLLER CORE IN 48 HOURS

Daniel Šulík - Milan Vasilko- Daniela Ďuračková - Peter Fuchs

   In this paper we present a design case study using Handel-C - a recently developed programming language for compilation of high-level programs directly into FPGA hardware. The design is an 8-bit RISC microcontroller core with 33 instructions, prescaler and a programmable timer. Handel-C was used throughout the entire design and debugging flow. The RISC microcontroller design was implemented on the XESS XS40 FPGA board with Xilinx XC4010XL FPGA. The overall design, including debugging, testing and the FPGA implementation was completed in less than 48 man-hours.

Keywords: Handel-C, RISC architecture, design methodology, FPGA, design flow

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