HIGH SPEED LOW POWER MULTI-THRESHOLD VOLTAGE FLIP FLOPS

Abdoul Rjoub - Ali Shatnawi

   Low-Power High-Speed Flip Flops (LPHSFF) are proposed in this paper. They are based on CMOS multi-threshold voltage techniques. High threshold voltage MOSFET transistors are applied on the on-critical paths of flip-flops in order to suppress the stand-by leakage-current, while low threshold voltage MOSFET transistors are applied on the cross-coupled critical path which in fact is the speed bottle neck of the flip-flip. This happened in order to increase the speed of operation of the circuit and to reduce the power dissipation. The proposed technique is usable in all types of flip-flops. Simulation results show the validity of the proposed technique to save power dissipation and to increase the speed of operation of the circuits. Using SPICE parameters of 0.25 um multi-threshold voltage CMOS technology, simulation results for 2.1 V supply voltage shown that 30% of power dissipation is reduced as the speed of operation is increased by 55%. Different applications are used to demonstrate the validity of the proposed technique.

Keywords: cross-coupled, critical path, multithreshold technique, leakage-current, low power design, high speed operation, memory cells, flip-flops, feedback output

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