TEST GENERATION BASED ON THE FUNCTIONALITY FAULT MODEL

Andrej Žemva - Baldomir Zajc

   In this paper, we present the functionality fault model and demonstrate its feasibility and advantages. In the current designs, the fanin of the modules implemented in CMOS standard cell, mask programmable or field-programmable gate array technology rarely exceeds 4 on the average. A functionality fault model based on the complete enumeration of the truth table of each logic module is thus entirely feasible and enhances the quality of the test significantly. Tests based on this model provide a complete module behavior, interior faults as well as input stuck-at and bridging faults of any multiplicity, reducing the need for technology and implementation-specific fault models. We have implemented the prototype software test-dc and demonstrate its application to generate high quality test patterns.

Keywords: fault modeling, don't cares, fault simulation, deterministic test pattern generation

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