EFFICIENT SYSTEM-LEVEL FUNCTIONAL VERIFICATION METHODOLOGY
Miroslav Čupák - Francky Catthoor - Hugo De Man
Today's multimedia applications represent complex systems
implemented on a single chip. Industrial experiments show that
the design of such applications has to start at the system-level in
order to fulfill increasing requirements for low power and
mininimum area of the final implementation. Typically, the
reduction of power and area of the chip includes a number of
sophisticated, but often manual optimisations applied on the
initial specification. Such optimisations are very error-prone.
Up to now, existing validation techniques have mainly
concentrated on verification at lower levels of design
abstraction. The verification at the system-level has not been fully
covered, and certainly not for complex loop nests.
In this paper, we propose a system-level methodology
functional verification of loop oriented transformations,
especially suited for multimedia applications. The methodology
is based on a combination of two complementary existing
techniques: formal verification of pure loop transformations and
SFG-tracing technique for verification of correctness of arithmetic
constructors and related control flow. The principles of our global
methodology are illustrated on a verification example.
Keywords: functional formal verification, algorithmic code transformations, low-power design