A NEW ARCHITECTURE OF DIGITAL FREQUENCY SYNTHESIZER

Milan Stork

   Frequency synthesis has many applications in today's commercial electronic and telecommunications system design. Some techniques exist which can be used to generate a frequency that is an integer or fractional multiple of a reference frequency. This paper describes architecture a new pure digital frequency synthesizer based on generators, counters and a register. The technique described here is much simpler then other method. Presented synthesizer is the most suitable for the design of VLSI architectures or for programmable Large Scale Integration. On the other hand, this synthesizer has a disadvantage in low output frequency.

Keywords: delay-locked loop, direct digital frequency, frequency synthesizer, phase locked loop, fractional phase locked loop

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