A HIGH-SPEED MULTIPLIER COPROCESSOR UNIT BASED ON FPGA

Alfredo Rosado - Javier Calpe - Manuel Bataller - Juan F. Guerrero - J. V. Francés

   Binary multiplication is an arithmetic operation widely used in digital signal processing applications such as filtering, digital control or communications. In order to achieve real-time performance, multiplication must be carried out as fast as possible, and thus higher clock rates are reached. A new architecture based on the L-Booth algorithm is proposed, and a high-speed 8x8 multiplier able to run at a clock rate of 51.8 MHz is developed and implemented on a Xilinx FPGA device. The external protocol to secure multiplier connection to a main processor can be easily implemented, and additional logic can be included within the same FPGA.

Keywords: multiplier, L-Booth algorithm, FPGA, real-time

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