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[1, 2013] 

Journal of Electrical Engineering, Vol 64, 1 (2013) 44-49; DOI: 10.2478/jee-2013-0006

A MULTI-ALPHABET ARITHMETIC CODING HARDWARE IMPLEMENTATION FOR SMALL FPGA DEVICES

Anton Biasizzo – Franc Novak – Peter Korošec

   Arithmetic coding is a lossless compression algorithm with variable-length source coding. It is more flexible and efficient than the well-known Huffman coding. In this paper we present a non-adaptive FPGA implementation of a multi-alphabet arithmetic coding with separated statistical model of the data source. The alphabet of the data source is a 256-symbol ASCII character set and does not include the special end-of-file symbol. No context switching is used in the proposed design which gives maximal throughput without pipelining. We have synthesized the design for Xilinx FPGA devices and used their built-in hardware resources.

Keywords: arithmetic coding, compression algorithm


[full-paper]


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