PLD MODELING OF ALL-DIGITAL DLL
Tomislav Švedek – Tomislav Matić – Marijan Herceg
An all-digital delay-locked loop (DLL) suitable for implementation in the programmable logic device (PLD) is presented in this paper. Analog parts of the conventional DLL are realized by digital circuitry. Digital-controlled delay line (DCDL) is made of programmable digital-controlled delay elements (DCDE) based on the binary-weighted multiplex LCELL structures. Problems encountered in PLD implementation of the DLL are emphasized and discussed. Simulation and measuring results of the proposed DLL realized by ALTERA device EPM7128SLI10, are presented.
Keywords: all-digital DLL, PLD implementation, digital-controlled delay line