IMPLEMENTATION OF A LEARNING SYNAPSE AND A NEURON FOR PULSE-COUPLED NEURAL NETWORKS

Pavol Tikovič - Marián Vörös - Daniela Ďuračková

   A new architecture of a learning synapse with on-chip learning and a neuron for pulse-coupled neural networks is presented. The main advantages of the proposed synapse are: continuous learning, easily adjustable parameters, compact design, low power and area consumption. This paper also contains results obtained from simulations performed with our model of a leaky integrate-and-fire neuron. The proposed neuron works with both constant or slowly changing input voltage level (input layer of a neural network) and pulse input (hidden layers and the output layer). Our circuits were designed in HSPICE and implemented in CAMELEON.

Keywords: pulse-coupled neural networks, continuous learning synapse, synaptic weight, Hebbian learning rule, integrate-and-fire neuron, threshold, action potential timing

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