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[07-08, 2005] 

Journal of Electrical Engineering, Vol 56, 07-08 (2005) 205-208


John E. Plevridis - Christos S. Koukourlis - John N. Sahalos

   A novel timing recovery technique is presented that can conciliate small noise bandwidth and provide good jitter suppression with a sufficient wide loop bandwidth. It is also suitable to maintain a stable recovered clock even if the input signal exhibits missing transitions. The technique utilizes two restorative control voltages derived from two closed loops, acting in parallel, for phase and frequency tracking. The first one is composed at the filter output of a conventional Phase Looked Loop (PLL). A Digital Loop derives the second control voltage by the aid of a Digital to Analog Converter (DAC) which retains frequency lock for the whole bandwidth. The basic idea of the combined analog- digital twin-loop architecture is presented and also benefits and design issues are depicted.

Keywords: clock recovery, synchronization, PLL


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