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[11-12, 2005] 

Journal of Electrical Engineering, Vol 56, 11-12 (2005) 298-305


Ali Shatnawi - Mohammed F. Shatnawi

   This paper deals with superscalar processors, which are capable of executing several instructions per clock cycle. Superscalar processors may be considered as the most promising uniprocessor architectures of the post RISC era. Although superscalar processors can be viewed as an evolution of the RISC architectures, they are subject to many more trade-offs than simply the pipeline depth. Executing more than one instruction per cycle embeds many problems. Among the most common problems that architects have to solve in superscalar architectures is the pipeline gaps due to control hazard. Control hazard results from the presence of conditional branches in programs. This problem has been addressed by several researchers during the last decade. In this paper, we present an efficient technique based on a combination of the Branch Target Buffer (BTB) and Predicated Execution. Simulation results show the effectiveness of the proposed method.

Keywords: superscalar processor, control hazard, branch prediction, predicated execution


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