advanced
Journal Information
Journal Information
   Description
   Editorial Board
   Guide for Authors
   Ordering

Contents Services
Contents Services
   Regular Issues
   Special Issues
   Authors Index

Links
Links
   FEI STU Bratislava
   SAS Bratislava

   Feedback

[5, 2015] 

Journal of Electrical Engineering, Vol 66, 5 (2015) 250-256 DOI: 10.1515/jee-2015-0041

DESIGN OF A 5-BIT FULLY PARALLEL ANALOG TO DIGITAL CONVERTER USING COMMON GATE DIFFERRENTIAL MOS PAIR-BASED COMPARATOR

Oktay Aytar

   This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (+0.63) LSB and (-0.26/+0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

Keywords: fully parallel A/D converter, common gate differential MOS pair, transmission gate based multiplexer circuit, high speed A/D converter


[full-paper]


© 1997-2020  FEI STU Bratislava